1. Field of Invention
The present invention relates to a method of manufacturing an integrated circuit device. More particularly, the present invention relates to a method of forming a polysilicon thin film transistor (poly-Si TFT) structure.
2. Description of Related Art
Thin film transistors are often used in active matrix liquid-crystalline devices (AMLCD) and static random access memory (SRAM). A thin film transistor can be classified as belonging to an amorphous silicon thin film type or a polysilicon thin film type. A polysilicon thin film transistor is able to provide higher carrier mobility and higher conductive current than an amorphous silicon thin film transistor. Furthermore, a polysilicon thin film transistor can be directly used in a peripheral circuit for forming the logic drivers of a display device. Since the driver circuit and the thin film transistor array can be fabricated on the same glass panel with a reduction of production cost, polysilicon thin film transistors are frequently used in liquid crystal display (LCD) panels. However, polysilicon thin film transistors generally produce a relatively large leakage current. In addition, the polysilicon thin film transistors must be able to attain a certain speed before they can be considered suitable for applications in logic circuit. Therefore, polysilicon thin film transistors are rarely used in large area liquid crystal display. To be incorporated inside a large area liquid crystal display, leakage current from the polysilicon thin film transistor must be reduced and operating speed of the transistor must be increased.
A major factor that may affect the amount of leakage current from a polysilicon thin film transistor includes the size of the electric field in the neighborhood of its drain terminal. To reduce leakage current, the electric field in the depletion region of a drain terminal must be reduced. The conventional method of reducing the electric field in the depletion region of a drain terminal is to produce a polysilicon thin film transistor with a lightly doped drain terminal or a gate-overlapped lightly doped drain.
Although the production of a lightly doped region between the drain terminal and the gate terminal of a polysilicon thin film transistor is able to reduce electric field in the depletion region and hence leakage current, electrical resistance is increased considerably in the lightly doped region. Hence, the amount of conductive current permitted to pass through the device is reduced and the response speed of the device is greatly lowered when the device is conductive.
In a polysilicon thin film transistor with a gate-overlapped lightly doped drain terminal, the lightly doped drain terminal is under the gate electrode so that the gate electrode and the lightly doped region overlap. In the conductive state, the gate electrode is able to sense the carriers in the lightly doped region, thereby lowering the resistance and maintaining a normal conductive current. In the non-conductive state, resistance is increased due to the expulsion of carriers from the lightly doped region by a gate voltage. Similarly, the electric field in the depletion region is lowered and leakage current is suppressed. However, in this type of structure, a highly conductive material such as polysilicon must be used to form the spacers. If, furthermore, metal silicide material is used to lower the resistance at a source/drain terminal, a conductive path is created between the gate electrode and the source/drain terminal. Hence, intrinsic properties of the device may be further damaged.
On the other hand, a principle factor that affects the operating speed of a polysilicon thin film transistor includes defects at polysilicon grain boundaries. Defects in these grain boundaries tend to trap carriers and set up regional potential barriers. By increasing the size of grains so that the number of crystal boundaries crossed per unit length is decreased, response speed of the polysilicon thin film transistor will increase considerably. The conventional method of increasing the size of polysilicon crystals includes solid phase crystallization (SPC), laser re-crystallization and metal-induced lateral crystallization (MILC).
To perform solid phase crystallization, a substrate with an amorphous silicon layer is placed inside a furnace. The furnace is heated to 600xc2x0 C. and the amorphous silicon layer is treated for a period of 24 hours so that the amorphous silicon is transformed into polysilicon. However, the high temperature treatment limits the type of material that can be used to form the bottom glass panel of a liquid crystal display. Hence, the production cost of the liquid crystal display panel is increased.
To perform a laser re-crystallization, a the amorphous silicon layer is scanned with a laser beam. Thermal energy produced by the laser beam re-crystallizes the amorphous silicon into polysilicon. Although re-crystallization temperature and defect density along the crystal boundaries are lowered, the polysilicon layer thus formed has a very rough surface which leads to intense dispersion at the interface between a polysilicon channel and a gate oxide layer. Ultimately, carrier mobility is greatly lowered. In addition, the polysilicon crystals resulting from laser re-crystallization are perpendicular to the channel and have a columnar form. Hence, size increase of crystals in a direction parallel to the channel is limited.
Metal-induced lateral crystallization (MILC) is a method capable of producing crystal growth in a direction parallel to the channel. After the completion of a conventional cap gate and gate production process, a metallic layer (for example, a nickel layer) is formed over the source/drain terminal. The wafer is heated to a temperature of about 500xc2x0 C. Utilizing the metal silicide above the source/drain terminal as a seed nucleus, crystals grow laterally from a source/drain region and extend into the channel region underneath the gate electrode. Under suitable growing conditions, lateral width of a crystal may be as long as 10xcexcm and carriers rarely encounter a crystal boundary when traversing the channel. However, in the process of forming the lateral crystals, a large number of defects are also created at the interface between the metal-induced crystals and the metal-induced lateral crystal so that operating speed of the device is lowered. To remove the interface between the metal-induced crystals and the metal-induced lateral crystal from the channel region, a masking procedure can be carried out. However, this extra step will increase production cost.
Accordingly, one object of the present invention is to provide a method of forming a polysilicon thin film transistor capable of reducing leakage current from the transistor and resistance at its source terminal, drain terminal and gate terminal. The method is further capable of improving the electrical properties of the transistor.
A second object of the invention is to provide a method of forming a polysilicon thin film transistor capable of reducing carrier mobility drop and hence current drop due to the crystal boundary crossing of carriers. Hence, operating speed of the transistor is increased and electrical properties of the transistor are improved.
A third object of the invention is to provide a method of forming a polysilicon thin film transistor having a double-layered spacer structure capable of suppressing leakage current and excluding its metal-induced crystal/metal-induced lateral crystal interface from its channel region at the same time. Although the interface contains more defects, the defect-ridden interface lies in the source/drain region without affecting any properties of the transistor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a polysilicon thin film transistor. First, an insulating substrate is provided. An amorphous channel layer is formed over the substrate. Photolithographic and etching techniques are used to pattern out an active region in the amorphous silicon channel layer. An oxide layer and a conductive layer are sequentially formed over the amorphous silicon channel layer. The conductive layer is patterned to form a gate electrode. Thereafter, using the gate electrode as a mask, a lightly doped source/drain region is formed in the amorphous silicon channel layer. A spacer that encloses the gate electrode is formed. A source/drain region is formed in the amorphous silicon channel layer. Using the spacer and the gate electrode as a mask, a portion of the oxide layer above the source/drain terminal is removed. Hence, an isolation spacer is formed on the sidewalls of the original spacer while the top section of the original spacer is exposed. A self-aligned silicide layer is formed over the top section of the original spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.
The spacer may be formed only on sidewalls of the gate electrode while exposing a top of the gate electrode, so that a self-aligned silicide is formed on the top of the gate electrode.
This invention also provides a polysilicon thin film transistor structure. The structure includes an insulating substrate and a metal-induced lateral crystallization polysilicon channel layer above the substrate. The metal-induced lateral crystallization polysilicon channel layer further includes a channel region, a lightly doped source/drain region and a source/drain region. The lightly doped source/drain region is adjacent to the channel region and the source/drain region is adjacent to the lightly doped source/drain region. An oxide layer lies above the metal-induced lateral crystallization polysilicon channel layer and covers both the channel region and the lightly doped source/drain region. A gate electrode is on the oxide layer inside the channel region. A first spacer covers the gate electrode entirely. A second spacer attaches to the sidewall of the first spacer. A self-aligned metal silicide layer lies on the top section of the first spacer and a portion of the exposed source/drain region.
The spacer may be formed only on sidewalls of the gate electrode while exposing a top of the gate electrode, so that a self-aligned silicide is formed on the top of the gate electrode.
One major aspect of this invention is the utilization of double-layered spacer technique and metal-induced lateral crystallization technique to fabricate a polysilicon thin film transistor. The transistor so formed has a smaller leakage current and a faster operating speed. Further, the interface between metal-induced crystallization region and metal-induced lateral crystallization region is excluded from the channel area so that any defects in the interface will not affect any operating properties of the transistor.
Leakage current from the transistor is greatly reduced by selectively depositing polysilicon or polysilicon-germanium material over the gate electrode to form a spacer that serves as a lightly doped drain structure over the gate electrode.
In addition, the application of a self-aligned technique to form a metal silicide layer over the gate electrode and the source/drain region reduces overall resistance at the gate and the source/drain terminal.
Furthermore, the metal silicide layer above the source/drain region is utilized to initiate a metal-induced lateral crystallization so that amorphous silicon within the channel layer is transformed into a lateral-crystallization-polysilicon channel layer. Ultimately, a channel with large crystals is produced and carrier mobility and hence operating speed is greatly increased. Moreover, the double-layered spacer structure permits the exclusion of the metal-induced crystallization/metal-induced lateral crystallization interface from the channel region. Although the interface may contain a great number of defects, the interface is located within the source/drain region. Hence, the transistor device is unaffected by such interface defects.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.